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Course Schedule
How to Register

Date Course City State Register Description
September
2017



Sep 4 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Sep 5-6 Embedded Systems Software Design (EMBD-SW) Orono (Minneapolis) MN Full Description
Sep 7 Custom PCIe training part 2 (FPGA CPCIE2) Minneapolis MN Private Description
Sep 7 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Orono (Minneapolis) MN Full Description
Sep 18-20 Designing with VHDL (LANG-VHDL) Orono (Minneapolis) MN Register Description
Sep 18-20 Designing with VHDL (LANG-VHDL) Online ONLINE Register Description
Sep 18-22 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Orono (Minneapolis) MN Register Description
Sep 18-22 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Online ONLINE Register Description
Sep 21-22 Advanced VHDL (LANG-ADV-VHDL) Orono (Minneapolis) MN Register Description
Sep 21-22 Advanced VHDL (LANG-ADV-VHDL) Online ONLINE Register Description
Sep 25-27 Designing with Verilog (LANG-VERILOG) Orono (Minneapolis) MN Register Description
Sep 25-27 Designing with Verilog (LANG-VERILOG) Online ONLINE Register Description
Sep 25-29 Designing with Verilog and SystemVerilog (LANG-VSV) Orono (Minneapolis) MN Register Description
Sep 25-29 Designing with Verilog and SystemVerilog (LANG-VSV) Online ONLINE Register Description
Sep 26-27 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Sep 28-29 Designing with SystemVerilog (LANG-SV-DES) Orono (Minneapolis) MN Register Description
Sep 28-29 Designing with SystemVerilog (LANG-SV-DES) Online ONLINE Register Description
October
2017



Oct 9 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Oct 10-11 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Schaumburg IL Register Description
Oct 10-11 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Oct 10-11 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Oct 12-13 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Oct 12-13 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Oct 17-18 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Oct 23-24 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Oct 23-25 Xilinx HLS and SDSoC (EMBD-HLS-SDSoC ) Schaumburg IL Register Description
Oct 25 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Oct 26-27 DSP Design Using System Generator (DSP-SYSGEN) Schaumburg IL Register Description
Oct 26-27 Essential DSP Implementation Techniques (DSP-20000) Schaumburg IL Register Description
Oct 30-Nov 1 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Orono (Minneapolis) MN Register Description
November
2017



Nov 2-3 Embedded Systems Software Design (EMBD-SW) Orono (Minneapolis) MN Register Description
Nov 6 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Orono (Minneapolis) MN Register Description
Nov 9 Zynq UltraScale+ MPSoC Webinar (WEB CUSTOM) Online ONLINE Private Description
Nov 13-15 Designing with VHDL (LANG-VHDL) Schaumburg IL Register Description
Nov 13-17 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Schaumburg IL Register Description
Nov 16-17 Advanced VHDL (LANG-ADV-VHDL) Schaumburg IL Register Description
Nov 20-21 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Minneapolis MN Register Description
Nov 23 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Nov 28-29 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Nov 30-Dec 1 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Orono (Minneapolis) MN Register Description
December
2017



Dec 4-6 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Orono (Minneapolis) MN Register Description
Dec 7-8 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Dec 18-19 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Dec 18-20 Xilinx HLS and SDSoC (EMBD-HLS-SDSoC ) Orono (Minneapolis) MN Register Description
Dec 20 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Register Description
Dec 25 Holiday (ENJOY-IT) Minneapolis MN Closed Description

How to Register

You may register online, by clicking on the "register" link next to the course, then filling out either the individual or group registration forms. You may also register by Phone or Email.  NPE accepts MasterCard, VISA, AMEX, Xilinx Training Credits or Corporate Purchase Orders. If you select a credit card, after filling out the registration form, you will be taken to our secure credit card payment page. Please select the class and the number of students to add to the cart before checking out. (Go to schedule)

Standard Course Pricing


Custom/Condensed Course Pricing


Student Cancellation Policy


NPE Course Cancellation Policy