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Course Schedule
How to Register

Date Course City State Register Description
March
2017



Mar 1-2 CUSTOM VIVADO TRAINING (VIVA10101) Rochester MN Private Description
Mar 7-10 VHDL Complete (LANG21040) Minneapolis MN Full Description
Mar 13-15 Zynq SoC Master Training for Experienced FPGA Designers (EMBD33040) Minneapolis MN Register Description
Mar 13-15 Zynq SoC Master Training for Experienced FPGA Designers (EMBD33040) Online ONLINE Register Description
Mar 15-16 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Minneapolis MN Closed Description
Mar 15-16 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Online ONLINE Closed Description
Mar 16-17 Designing with SystemVerilog (LANG14000) Minneapolis MN Full Description
Mar 20-21 DSP Design Using System Generator (DSP-SYSGEN) Schaumburg IL Closed Description
Mar 20-21 Essential DSP Implementation Techniques (DSP20000) Schaumburg IL Closed Description
Mar 22-23 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP21000) Schaumburg IL Full Description
Mar 22-24 Xilinx HLS and SDSoC (EMBD HLS SDSOC CUSTOM) Schaumburg IL Closed Description
Mar 22-24 Vivado Design Suite Advanced XDC and Timing Analysis (VIVA11000) Schaumburg IL Closed Description
Mar 24 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD SDSOC) Schaumburg IL Full Description
April
2017



Apr 3-5 Designing with Verilog (LANG12000) Minneapolis MN Register Description
Apr 4-7 VHDL Complete (LANG21040) Minneapolis MN Register Description
Apr 6-7 Designing with SystemVerilog (LANG14000) Minneapolis MN Register Description
Apr 10-11 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Apr 12-13 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Apr 12-14 Vivado Design Suite Advanced XDC and Timing Analysis (VIVA11000) Minneapolis MN Register Description
Apr 18-19 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Schaumburg IL Register Description
Apr 24-25 DSP Design Using System Generator (DSP-SYSGEN) Naperville IL Register Description
Apr 24-25 Essential DSP Implementation Techniques (DSP20000) Naperville IL Register Description
Apr 26-28 Vivado Design Suite Advanced XDC and Timing Analysis (VIVA11000) Schaumburg IL Register Description
May
2017



May 9-11 Designing with Multi-Gigabit Serial I/O (RIO22000) Schaumburg IL Full Description
May 9-10 Designing a LogiCORE PCI Express System (PCIE28000) Schaumburg IL Register Description
May 9-11 Zynq SoC Master Training for Experienced FPGA Designers (EMBD33040) Schaumburg IL Register Description
May 22-23 Embedded Design with PetaLinux Tools (EMBD22000) Minneapolis MN Register Description
May 22-23 Essential DSP Implementation Techniques (DSP20000) Schaumburg IL Register Description
May 24-25 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP21000) Minneapolis MN Register Description
May 24-26 Xilinx HLS and SDSoC (EMBD HLS SDSOC CUSTOM) Schaumburg IL Register Description
May 26 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD SDSOC) Schaumburg IL Register Description
June
2017



Jun 5-6 C Language Programming with SDK (EMBD12000) Minneapolis MN Register Description
Jun 7-8 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Minneapolis MN Register Description
Jun 15-16 Embedded Design with PetaLinux Tools (EMBD22000) Minneapolis MN Register Description
Jun 19-20 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Schaumburg IL Register Description
Jun 21-22 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP21000) Schaumburg IL Register Description
Jun 21-23 Xilinx HLS and SDSoC (EMBD HLS SDSOC CUSTOM) Schaumburg IL Register Description
Jun 23 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD SDSOC) Schaumburg IL Full Description
Jun 26-28 Designing with VHDL (LANG11000) Minneapolis MN Register Description
Jun 26-28 Designing with VHDL (LANG11000) Online ONLINE Register Description
Jun 29-30 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Minneapolis MN Register Description
July
2017



Jul 17-18 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Jul 19-20 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description

How to Register

You may register online, by clicking on the "register" link next to the course, then filling out either the individual or group registration forms. You may also register by Phone or Email.  NPE accepts MasterCard, VISA, AMEX, Xilinx Training Credits or Corporate Purchase Orders. If you select a credit card, after filling out the registration form, you will be taken to our secure credit card payment page. Please select the class and the number of students to add to the cart before checking out. (Go to schedule)

Standard Course Pricing


Custom/Condensed Course Pricing


Student Cancellation Policy


NPE Course Cancellation Policy