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Course Schedule
How to Register

Date Course City State Register Description
May
2018



May 2 Custom Vivado and Stataic Timing Training Part 1 (FPGA CUSTOM STA P1) Minneapolis MN Register Description
May 3 Essentials of Microprocessors (EMBD-uPS) Online ONLINE Register Description
May 4 Custom Vivado and Stataic Timing Training Part 2 (FPGA CUSTOM STA P2) Minneapolis MN Register Description
May 8-9 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) St Louis MO Register Description
May 10-11 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) St Louis MO Register Description
May 15-16 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Closed Description
May 15-16 DSP Design Using System Generator (DSP-SYSGEN) Schaumburg IL Closed Description
May 15-16 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Full Description
May 16 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
May 17-18 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Orono (Minneapolis) MN Register Description
May 17-18 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Schaumburg IL Full Description
May 21-23 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Overland Park KS Full Description
May 21 Custom Partial Reconfiguration Training (FPGA-CUSTOM-PR) Orono (Minneapolis) MN Full Description
May 22-23 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) St Louis MO Full Description
May 23-25 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) St Louis MO Full Description
May 24-25 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
May 28 Holiday (ENJOY-IT) Minneapolis MN Closed Description
May 29-30 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Orono (Minneapolis) MN Register Description
May 30-Jun 1 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Orono (Minneapolis) MN Register Description
May 30-31 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Overland Park KS Register Description
May 30-Jun 1 VDES1 with Custom selected topics in Vivadao, STA, XDC, IPI (CP-CSTIVSXI) Overland Park KS Register Description
June
2018



Jun 1 Custom selected topics in Vivadao, STA, XDC, IPI (CP-CSTIVSXI1D) Overland Park KS Register Description
Jun 8 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Register Description
Jun 11-13 Designing with Verilog (LANG-VERILOG) Milwaukee WI Full Description
Jun 11-15 Designing with Verilog and SystemVerilog (LANG-VSV) Milwaukee WI Full Description
Jun 11-15 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Schaumburg IL Register Description
Jun 11-12 Essential DSP Implementation Techniques (DSP-ESS) Orono (Minneapolis) MN Register Description
Jun 14-15 Designing with SystemVerilog (LANG-SV-DES) Milwaukee WI Full Description
Jun 18-19 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Jun 18-19 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Omaha NE Register Description
Jun 20-22 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Omaha NE Register Description
Jun 21-22 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Omaha NE Register Description
Jun 21-22 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Cedar Rapids IA Register Description
Jun 25-27 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Orono (Minneapolis) MN Register Description
Jun 25-26 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Jun 25-26 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Jun 27 Essentials of Microprocessors (EMBD-uPS) Orono (Minneapolis) MN Register Description
Jun 28-29 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Jun 28-29 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
July
2018



Jul 2-3 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Online ONLINE Register Description
Jul 4 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Jul 5-6 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Online ONLINE Register Description
Jul 6 Essentials of Microprocessors (EMBD-uPS) Online ONLINE Register Description
Jul 9-11 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Overland Park KS Register Description
Jul 9-10 Embedded Systems Software Design (EMBD-SW) Overland Park KS Register Description
Jul 9-10 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Jul 11-13 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Overland Park KS Register Description
Jul 11 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Jul 12-13 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Overland Park KS Register Description
Jul 16-20 Custom US and US+ training (CUST-US) Minneapolis MN Full Description
Jul 23-27 Custom US and US+ training (CUST-US) Milwaukee WI Full Description
Jul 30-31 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Orono (Minneapolis) MN Register Description
Jul 30-31 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Jul 30-31 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Omaha NE Register Description
Jul 30-31 Designing a LogiCORE PCI Express System (CONN-PCIe) Schaumburg IL Register Description
August
2018



Aug 2-3 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Omaha NE Register Description
Aug 2-3 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Register Description
Aug 6-7 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
Aug 6-8 Designing with VHDL (LANG-VHDL) St Louis MO Register Description
Aug 6-10 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) St Louis MO Register Description
Aug 6-7 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Online ONLINE Register Description
Aug 9-10 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Online ONLINE Register Description
Aug 9-10 Advanced VHDL (LANG-ADV-VHDL) St Louis MO Register Description
Aug 13-14 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
Aug 13-14 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Aug 15 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Aug 15-16 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Aug 16-17 Essential DSP Implementation Techniques (DSP-ESS) Orono (Minneapolis) MN Register Description
Aug 16-17 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Aug 16-17 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Schaumburg IL Register Description
Aug 17 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Schaumburg IL Register Description
Aug 20-21 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Aug 20-21 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Aug 22-24 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Schaumburg IL Register Description
Aug 23-24 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Aug 27-29 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Omaha NE Register Description
Aug 30-31 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
September
2018



Sep 3 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Sep 6-7 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Omaha NE Register Description
Sep 10-12 Designing with VHDL (LANG-VHDL) Online ONLINE Register Description
Sep 10-14 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Online ONLINE Register Description
Sep 13-14 Advanced VHDL (LANG-ADV-VHDL) Online ONLINE Register Description

How to Register

You may register online, by clicking on the "register" link next to the course, then filling out either the individual or group registration forms. You may also register by Phone or Email.  NPE accepts MasterCard, VISA, AMEX, Xilinx Training Credits or Corporate Purchase Orders. If you select a credit card, after filling out the registration form, you will be taken to our secure credit card payment page. Please select the class and the number of students to add to the cart before checking out. (Go to schedule)

Standard Course Pricing


Custom/Condensed Course Pricing


Student Cancellation Policy


NPE Course Cancellation Policy