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Course Schedule
How to Register

Date Course City State Register Description
January
2018



Jan 3-5 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Online ONLINE Full Description
Jan 8-12 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Online ONLINE Register Description
Jan 8-10 Designing with VHDL (LANG-VHDL) Online ONLINE Register Description
Jan 11-12 Advanced VHDL (LANG-ADV-VHDL) Online ONLINE Register Description
Jan 15-16 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Online ONLINE Register Description
Jan 17 Essentials of Microprocessors (EMBD-uPS) Orono (Minneapolis) MN Full Description
Jan 18-19 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Online ONLINE Register Description
Jan 22-23 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Jan 24 Essentials of Microprocessors (EMBD-uPS) Schaumburg IL Register Description
Jan 25-26 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Jan 29-31 Xilinx HLS and SDSoC (EMBD-HLSSDSoC ) Schaumburg IL Register Description
Jan 29-30 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Jan 31 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
February
2018



Feb 1-2 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Orono (Minneapolis) MN Register Description
Feb 1-2 Essential DSP Implementation Techniques (DSP-ESS) Online ONLINE Register Description
Feb 5-6 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) St Louis MO Register Description
Feb 5-7 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Orono (Minneapolis) MN Register Description
Feb 5-7 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Online ONLINE Register Description
Feb 8-9 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) St Louis MO Register Description
Feb 12-13 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) St Louis MO Register Description
Feb 12-14 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Overland Park KS Register Description
Feb 12-13 Embedded Systems Software Design (EMBD-SW) Orono (Minneapolis) MN Register Description
Feb 14-15 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Feb 15-16 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Orono (Minneapolis) MN Register Description
Feb 15-16 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) St Louis MO Register Description
Feb 19-20 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
Feb 19-20 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) St Louis MO Register Description
Feb 19-20 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Feb 19-21 Xilinx HLS and SDSoC (EMBD-HLSSDSoC ) Orono (Minneapolis) MN Register Description
Feb 21-22 Designing with Xilinx Serial Transceivers (CONN-TRX) Orono (Minneapolis) MN Register Description
Feb 21-22 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Minneapolis MN Register Description
Feb 21 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Register Description
Feb 22-23 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Schaumburg IL Register Description
Feb 23 Essentials of Microprocessors (EMBD-uPS) Online ONLINE Register Description
Feb 26-28 Designing with Verilog (LANG-VERILOG) Milwaukee WI Register Description
Feb 26-Mar 2 Designing with Verilog and SystemVerilog (LANG-VSV) Milwaukee WI Register Description
Feb 26-28 Designing with VHDL (LANG-VHDL) Online ONLINE Register Description
Feb 26-Mar 2 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Online ONLINE Register Description
March
2018



Mar 1-2 Designing with SystemVerilog (LANG-SV-DES) Milwaukee WI Register Description
Mar 1-2 Advanced VHDL (LANG-ADV-VHDL) Online ONLINE Register Description
Mar 5-6 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Orono (Minneapolis) MN Register Description
Mar 6-7 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Mar 7-8 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Minneapolis MN Register Description
Mar 8-9 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Champaign IL Register Description
Mar 12-13 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Minneapolis MN Register Description
Mar 13-14 Embedded Design with PetaLinux Tools (EMBD-PLNX) St Louis MO Register Description
Mar 14-15 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Mar 19-21 Xilinx HLS and SDSoC (EMBD-HLSSDSoC ) Orono (Minneapolis) MN Register Description
Mar 19-20 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Orono (Minneapolis) MN Register Description
Mar 21 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Orono (Minneapolis) MN Register Description
Mar 26-27 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Register Description
April
2018



Apr 2-3 Zynq UltraScale+ MPSoC for the System Architect (EMBD-ZUPSA) Schaumburg IL Register Description
Apr 4-5 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Schaumburg IL Register Description
Apr 5-6 DSP Design Using System Generator (DSP-SYSGEN) Schaumburg IL Register Description
Apr 5-6 Designing with the 7 Series Families (FPGA-7SERIES) Schaumburg IL Register Description
Apr 9-10 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Online ONLINE Register Description
Apr 10-11 Embedded Design with PetaLinux Tools (EMBD-PLNX) Orono (Minneapolis) MN Register Description
Apr 12-13 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Online ONLINE Register Description
Apr 12-13 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
Apr 16-17 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Apr 16-17 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Online ONLINE Register Description
Apr 19-20 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Online ONLINE Register Description
Apr 19-20 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Apr 24-25 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Apr 24-26 Xilinx HLS and SDSoC (EMBD-HLSSDSoC ) Schaumburg IL Register Description
Apr 26 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Apr 26-27 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description

How to Register

You may register online, by clicking on the "register" link next to the course, then filling out either the individual or group registration forms. You may also register by Phone or Email.  NPE accepts MasterCard, VISA, AMEX, Xilinx Training Credits or Corporate Purchase Orders. If you select a credit card, after filling out the registration form, you will be taken to our secure credit card payment page. Please select the class and the number of students to add to the cart before checking out. (Go to schedule)

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NPE Course Cancellation Policy