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Course Schedule
How to Register

Date Course City State Register Description
July
2018



Jul 2-3 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
Jul 4 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Jul 5-6 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Jul 6 Essentials of Microprocessors (EMBD-uPS) Orono (Minneapolis) MN Register Description
Jul 9-10 Embedded Systems Software Design (EMBD-SW) Orono (Minneapolis) MN Register Description
Jul 9-10 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Jul 11-13 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Schaumburg IL Register Description
Jul 11 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Full Description
Jul 12-13 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Full Description
Jul 16-20 Custom US and US+ training (CUST-US) Minneapolis MN Full Description
Jul 23-27 Custom US and US+ training (CUST-US) Milwaukee WI Full Description
Jul 30-31 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Orono (Minneapolis) MN Register Description
Jul 30-31 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Jul 30-31 Designing a LogiCORE PCI Express System (CONN-PCIe) Schaumburg IL Closed Description
Jul 30-Aug 1 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Schaumburg IL Register Description
August
2018



Aug 2-3 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Orono (Minneapolis) MN Register Description
Aug 6-7 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Orono (Minneapolis) MN Register Description
Aug 8-10 Designing with VHDL (LANG-VHDL) Schaumburg IL Register Description
Aug 9-10 DSP Design Using System Generator (DSP-SYSGEN) Orono (Minneapolis) MN Register Description
Aug 9-10 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Aug 13-14 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
Aug 13-14 Advanced VHDL (LANG-ADV-VHDL) Schaumburg IL Register Description
Aug 13-14 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP-HLS) Schaumburg IL Register Description
Aug 13 Advanced Features and Techniques of Embedded Systems Software Design (EMBD-ADVSW) Schaumburg IL Register Description
Aug 15 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD-SDSOC) Schaumburg IL Register Description
Aug 15-16 Embedded Systems Software Design (EMBD-SW) Schaumburg IL Register Description
Aug 16-17 Essential DSP Implementation Techniques (DSP-ESS) Orono (Minneapolis) MN Register Description
Aug 16-17 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Aug 20-21 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Omaha NE Register Description
Aug 20-21 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Aug 20-21 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Aug 22-24 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (FPGA-STAXDCADV) Schaumburg IL Register Description
Aug 22-24 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Orono (Minneapolis) MN Register Description
Aug 23-24 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Aug 27-29 Zynq SoC Master Training for Experienced FPGA Designers (EMBD-33040) Omaha NE Register Description
Aug 27-28 Advanced SDSoC Development Environment and Methodology (EMBD-ADVSDSOC) Schaumburg IL Register Description
Aug 30-31 Embedded Design with PetaLinux Tools (EMBD-PLNX) Schaumburg IL Register Description
Aug 30-31 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Orono (Minneapolis) MN Register Description
September
2018



Sep 3 Holiday (ENJOY-IT) Minneapolis MN Closed Description
Sep 6-7 Xilinx Partial Reconfiguration Tools and Techniques (FPGA-PR) Schaumburg IL Register Description
Sep 10-12 Designing with VHDL (LANG-VHDL) Schaumburg IL Register Description
Sep 10-14 VHDL and Advanced VHDL using the Vivado Design Suite (FPGA-VHDLADVVHDLVDS) Schaumburg IL Register Description
Sep 13-14 Advanced VHDL (LANG-ADV-VHDL) Schaumburg IL Register Description

How to Register

You may register online, by clicking on the "register" link next to the course, then filling out either the individual or group registration forms. You may also register by Phone or Email.  NPE accepts MasterCard, VISA, AMEX, Xilinx Training Credits or Corporate Purchase Orders. If you select a credit card, after filling out the registration form, you will be taken to our secure credit card payment page. Please select the class and the number of students to add to the cart before checking out. (Go to schedule)

Standard Course Pricing


Custom/Condensed Course Pricing


Student Cancellation Policy


NPE Course Cancellation Policy