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Course Schedule
How to Register

Date Course City State Register Description
May
2017



May 1-3 Designing with Verilog (LANG12000) Minneapolis MN Register Description
May 4-5 Designing with SystemVerilog (LANG14000) Minneapolis MN Register Description
May 12 Debugging Techniques Using the Vivado Logic Analyzer (FPGA21000) Schaumburg IL Register Description
May 15-16 DSP Design Using System Generator (DSP-SYSGEN) Minneapolis MN Register Description
May 17-19 Zynq SoC Master Training for Experienced FPGA Designers (EMBD33040) Minneapolis MN Register Description
May 22-23 Embedded Design with PetaLinux Tools (EMBD22000) Schaumburg IL Register Description
May 24-26 Designing with Verilog (LANG12000) Schaumburg IL Register Description
May 29-30 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Online ONLINE Register Description
June
2017



Jun 1-2 C Language Programming with SDK (EMBD12000) Minneapolis MN Register Description
Jun 5-6 Embedded Design with PetaLinux Tools (EMBD22000) Minneapolis MN Register Description
Jun 19-20 Designing a LogiCORE PCI Express System (PCIE28000) Schaumburg IL Register Description
Jun 19-20 Essential DSP Implementation Techniques (DSP20000) Schaumburg IL Register Description
Jun 19-20 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Schaumburg IL Register Description
Jun 21-23 Designing with Multi-Gigabit Serial I/O (RIO22000) Schaumburg IL Register Description
Jun 21-22 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP21000) Schaumburg IL Register Description
Jun 21-23 Xilinx HLS and SDSoC (EMBD HLS SDSOC CUSTOM) Schaumburg IL Register Description
Jun 23 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD SDSOC) Schaumburg IL Register Description
Jun 26-28 Designing with VHDL (LANG11000) Minneapolis MN Register Description
Jun 26-28 Designing with VHDL (LANG11000) Online ONLINE Register Description
Jun 26-27 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Minneapolis MN Register Description
Jun 29-30 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Minneapolis MN Register Description
July
2017



Jul 10-11 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Minneapolis MN Register Description
Jul 13-14 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Schaumburg IL Register Description
Jul 17-18 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Schaumburg IL Register Description
Jul 19-20 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Schaumburg IL Register Description
Jul 19-21 STA, XDC, and Advanced Tools and Techniques of Vivado Design Suite-custom (VIVA33050) Schaumburg IL Register Description
Jul 21 Debugging Techniques Using the Vivado Logic Analyzer (FPGA21000) Schaumburg IL Register Description
Jul 24-25 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Schaumburg IL Register Description
Jul 26-28 Vivado Design Suite Advanced XDC and Timing Analysis (VIVA11000) Schaumburg IL Register Description
August
2017



Aug 2-4 Zynq SoC Master Training for Experienced FPGA Designers (EMBD33040) Schaumburg IL Register Description
Aug 10-11 Designing FPGAs Using the Vivado Design Suite 1 (FPGA-VDES1) Minneapolis MN Register Description
Aug 14-15 Embedded Design with PetaLinux Tools (EMBD22000) Minneapolis MN Register Description
Aug 14-16 Zynq SoC Master Training for Experienced FPGA Designers (EMBD33040) Minneapolis MN Register Description
Aug 16-17 C-based Design: High-Level Synthesis with the Vivado HLS Tool (DSP21000) Minneapolis MN Register Description
Aug 16-18 Xilinx HLS and SDSoC (EMBD HLS SDSOC CUSTOM) Schaumburg IL Register Description
Aug 17-18 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Register Description
Aug 18 Embedded C/C++ SDSoC Development Environment and Methodology (EMBD SDSOC) Schaumburg IL Register Description
Aug 21-22 Designing FPGAs Using the Vivado Design Suite 2 (FPGA-VDES2) Minneapolis MN Register Description
Aug 21-23 Vivado Design Suite Advanced XDC and Timing Analysis (VIVA11000) Minneapolis MN Register Description
Aug 23-24 Designing with the UltraScale and UltraScale+ Architectures (FPGA-US) Minneapolis MN Register Description
Aug 24-25 Designing FPGAs Using the Vivado Design Suite 3 (FPGA-VDES3) Minneapolis MN Register Description
Aug 31-Sep 1 Designing FPGAs Using the Vivado Design Suite 4 (FPGA-VDES4) Minneapolis MN Register Description

How to Register

You may register online, by clicking on the "register" link next to the course, then filling out either the individual or group registration forms. You may also register by Phone or Email.  NPE accepts MasterCard, VISA, AMEX, Xilinx Training Credits or Corporate Purchase Orders. If you select a credit card, after filling out the registration form, you will be taken to our secure credit card payment page. Please select the class and the number of students to add to the cart before checking out. (Go to schedule)

Standard Course Pricing


Custom/Condensed Course Pricing


Student Cancellation Policy


NPE Course Cancellation Policy